The present invention relates to a priority circuit (priority encoding circuit) used for obtaining a binary address output by encoding a plurality of identify address signals of a content addressable memory (CAM) or the like in accordance with predetermined priority levels.
Conventional priority circuits will now be described with reference to drawings.
FIG. 8 shows a conventional priority circuit that receives three input signals IN0, IN1 and IN2 and is operated through control in accordance with clocks C1, C2 and C3 so as to output three binary output signals OUT0, OUT1 and OUT2 as a result of given priority processing of the input signals.
This priority circuit has what is called an active L circuit configuration in which when any of the input signals is at H level, a L-level signal is output to an output terminal HIT, which means that the input signals include a H-level signal, and a H-level signal is output to merely an output terminal corresponding to an input terminal with the highest priority level out of the input terminals having received H-level signals. In this case, the priority level is highest in the lowest portion of the drawing and is lowered toward the upper portion thereof.
In FIG. 8, a reference numeral 800 denotes the priority circuit and a reference numeral 801 denotes a priority circuit element included in the priority circuit 800, and this priority circuit 800 includes three priority circuit elements respectively correspondingly to the three inputs. Reference numerals 8020, 8021 and 8022 denote NMOS transistors for input control, each of which is simultaneously controlled in accordance with the clock signal C1 input to the gate thereof. Thus, when the clock signal C1 is at H level, the input signals are transferred to internal nodes Q0, Q1 and Q2 of the priority circuit.
On the other hand, reference numerals 8040, 8041 and 8042 denote PMOS transistors serially connected between H potential and the output terminal HIT. The source of the PMOS transistor 8040 with the highest priority level is connected to the H potential, and the drain of the PMOS transistor 8042 with the lowest priority level is connected to the output terminal HIT. In each of the transistors, source potential is transferred to its drain when the signal input to its gate is at L level. At this point, the sources of the PMOS transistors 8040, 8041 and 8042 are respectively designated as propagating signal nodes P0, P1 and P2. Reference numerals 8030, 8031 and 8032 denote NMOS transistors whose sources are grounded and whose drains are connected to the drains of the PMOS transistors 8040, 8041 and 8042, respectively. The gates of the NMOS transistors 8030, 8031 and 8032 and the PMOS transistors 8040, 8041 and 8042 are respectively connected to the nodes Q0, Q1 and Q2 so as to receive the input signals. In accordance with the input signals, the NMOS and PMOS transistors are exclusively controlled.
Also, reference numerals 8050, 8051 and 8052 denote two-input AND circuits respectively having one input terminals connected to the nodes Q0, Q1 and Q2 and the other input terminals connected to the sources of the PMOS transistors 8040, 8041 and 8042. Thus, logical products of the inputs are output to the output terminals OUT0, OUT1 and OUT2 as binary address signals.
Furthermore, reference numerals 8060, 8061 and 8062 denote reset circuits. Since the reset circuits included in the respective priority circuit elements have the identical configuration, the configuration of the reset circuit 8061 alone will be herein described. The reset circuit 8061 includes three NMOS transistors 8061a, 8061b and 8061c. The source and the drain of the NMOS transistor 8061a are connected between the output terminal OUT1 and the gate of the NMOS transistor 8061b, and the NMOS transistors 8061c and 8061b are serially connected between the node Q1 and the ground. Also, the gate of the NMOS transistor 8061a is connected to the clock terminal C3 and the gate of the NMOS transistor 8061c is connected to the clock terminal C2. The signals input from these two clock terminals C2 and C3 (hereinafter referred to as the clock signals C2 and C3) are used for simultaneously controlling the priority circuit elements similarly to the clock signal C1.
Owing to this configuration, in the case where the input signal IN1 and potential on the node Q1 are at H level and potential on the propagating signal node P1 is at H level, namely, in the case where the signal on the output terminal OUT1 is at H level, when the clock signal C3 is at H level, the NMOS transistor 8061a is turned on so as to transfer the H potential of the output terminal OUT1 to the gate of the NMOS transistor 8061b. Therefore, the NMOS transistor 8061b is turned on. At this point, when the clock signal C2 is at H level, the NMOS transistors 8061b and 8061c, are both turned on, and hence, the node Q1 is reset to L potential. Alternatively, in the case where the input signal IN1 and the potential on the node Q1 are at L level, namely, in the case where the signal on the output terminal OUT1 is at L level, when the clock signal C3 is at H level, the NMOS transistor 8061a is turned on so as to transfer the L potential of the output terminal OUT1 to the gate of the NMOS transistor 8061b. Therefore, the NMOS transistor 8061b is turned off, and hence, the clock signal C2 undergoes a H transition. As a result, even when the NMOS transistor 8061c is turned on, the potential on the node Q1 is kept at L level.
Next, as an example of the case where a plurality of H-level signals are input to the input terminals IN0, IN1 and IN2 (hereinafter signals input to these input terminals are designated as input signals IN0, IN1 and IN2), an operation performed when the input signal IN0 is at L level and the input signals IN1 and IN2 are equal to each other and at H level will be described.
In this case, the clock signal C1 first undergoes a H transition, and the NMOS transistors 8020, 8021 and 8022 are turned on. Therefore, signals on the nodes Q0, Q1 and Q2 are at L, H and H level, respectively, the PMOS transistors 8040, 8041 and 8042 are placed in an on state, an off state and an off state, respectively, and the NMOS transistors 8030, 8031 and 8032 are placed in an off state, an on state and an on state, respectively. Accordingly, potentials on the propagating signal nodes P0, P1 and P2 and the output terminal HIT are at H, H, L and L level, respectively. Therefore, as a result of the operations performed by the AND circuits 8050, 8051 and 8052, signals on the output terminals OUT0, OUT1 and OUT2 undergo a L transition, a H transition and a L transition, respectively. This means that the second terminal has the highest priority level out of the input terminals having received the H-level signals.
Next, potentials on the nodes Q0, Q1 and Q2 are set to L, L and H level, respectively by the reset circuits 8060, 8061 and 8062 receiving these output signals at L, H and L level and the clock signals C2 and C3, namely, merely the node Q1 corresponding to the H-level output signal is rest, so that the corresponding output signal undergoes a H to L transition. Thus, the PMOS transistor 8041 is turned on and the NMOS transistor 8031 is turned off, and therefore, the potentials on the propagating signal nodes P0, P1 and P2 and the output terminal HIT are set to H, H, H and L level, respectively. In other words, the H-level propagating signal is propagated to the propagating signal node P2, the output signals OUT0, OUT1 and OUT2 respectively at L, L and H level are output through the operations of the AND circuits 8050, 8051 and 8052, and it is found, as a result of the aforementioned reset operation, that the H-level input having the second highest priority level corresponds to the third input signal IN2.
In this manner, even in the case where a plurality of H-level signals are input to the signal input terminals IN0, IN1 and IN2, signals with higher priority levels are successively selected, merely one H-level signal is output to one of the output terminals OUT0, OUT1 and OUT2, and it is indicated by outputting a signal at L (active L) level to the output terminal HIT that that at least one H-level signal is input to any of the nodes Q0, Q1 and Q2. Even when the number of input signals is further increased, a similar operation may be performed by additionally providing the priority circuit elements 801. This priority circuit is disclosed in Japanese Laid-Open Patent Publication No. 60-59595.
A conventional priority circuit 900 shown in FIG. 9 can perform similar priority processing but is different from the priority circuit 800 of FIG. 8 as follows: The PMOS transistors 8040, 8041 and 8042 are respectively replaced with NMOS transistors 9040, 9041 and 9042; the NMOS transistors 8030, 8031 and 8032 are respectively replaced with PMOS transistors 9030, 9031 and 9032; the AND circuits 8050, 8051 and 8052 are respectively replaced with NOR circuits 9050, 9051 and 9052; inverters 9070, 9071 and 9072 are additionally provided respectively between the nodes Q0, Q1 and Q2 and the gates of the NMOS transistors 9040, 9041 and 9042 and the PMOS transistors 9030, 9031 and 9032; and the propagating signal node P0 is fixed to L level instead of H level. However, the priority circuit 900 has an active H configuration in which the output terminal HIT outputs a H-level signal when a H-level signal is input to any of the input terminals, namely, when a HIT signal is detected.
In general, when transistors have the same size, a node potential can be lowered from VDD potential to 0 V by turning an NMOS transistor on faster than increasing a node potential from 0 V to the VDD potential by turning a PMOS transistor on. Therefore, the priority circuit 900 of FIG. 9 can perform the priority processing faster than the priority circuit 800 of FIG. 8.
A conventional priority circuit 1000 shown in FIG. 10 is different from the priority circuit 900 of FIG. 9 in a portion for performing the logic operation connected to the output terminals. In the priority circuit of FIG. 9, results of the logic operation performed by the NOR circuits on inverted signals of the input signals and the potentials on the propagating signal nodes are output as the output signals OUT0, OUT1 and OUT2. In contrast, in the priority circuit of FIG. 10, results of logic operation performed by AND circuits receiving inverted signals of potentials on propagating signal nodes on the input side of the priority circuit elements and potentials on propagating signal nodes on the output side are output as output signals OUT0, OUT1 and OUT2. The operation of the priority circuit of FIG. 10 is the same as that of the priority circuit of FIG. 9.
However, in the conventional configuration of FIG. 10, for example, in the case where the input signals IN0, IN1 and IN2 are respectively at H, L and L level and potentials on the propagating signal nodes P0, P1 and P2 and the output terminal HIT are respectively at L, H, H and H level, the H-level signal is transferred from the propagating signal node P1 to the propagating signal node P2 or from the propagating signal node P2 to the output terminal HIT through an NMOS transistor 10041 or 10042. Therefore, the propagated signal is lowered in its voltage correspondingly to the threshold voltages of the NMOS transistors 10041 and 10042. As a result, the H-level signal cannot attain desired high potential but is harmfully affected by noise or the like. Also, when the number of input signals is increased, the speed of the priority processing is disadvantageously lowered because the number of serially connected NMOS transistors is also increased.
Furthermore, in order to detect input signals including two or more H-level signals, it is necessary to reset the nodes Q0, Q1 and Q2 by using the clock signals C2 and C3 and the output signals OUT0, OUT1 and OUT2 every time one H-level signal with second or lower priority level is detected. Therefore, such processing cannot be completed in one cycle.
These problems also occur in the priority circuits of FIGS. 8 and 9 using signals with different polarities.